HENDERSON, Nev., 19 June 2014. Elbit Systems Ltd. engineers employed Aldec Inc.’s DO-254/CTS as the primary FPGA physical testing platform for a project that has just passed a critical European Aviation Safety Agency (EASA) verification audit.
“FPGA requirements-based testing is critical to DO-254 compliance, but in most cases not feasible to do in the target board due to the lack of FPGA input control and output access points; this created major challenges for Elbit,” says Aldec DO-254 Program Manager Louie De Luna. “DO-254/CTS solved Elbit’s major challenges and they were able to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used its simulation testbench as test vectors for FPGA at-speed testing which cut their development costs.”
Elbit’s project included multiple field-programmable gate arrays (FPGAs), each with multiple clock domains and high speed interfaces to PCI, ARINC, and LVDS. Elbit verified FPGA pin-level requirements using DO-254/CTS custom boards and verified board-level requirements using a target board. By deploying Aldec’s DO-254/CTS in their verification flow, Elbit increased functional verification coverage by test and reduced the overall verification cycle, according to a spokesperson. EASA supported Elbit’s FPGA testing approach facilitated by Aldec’s DO-254/CTS.
“EASA approved our verification process based on Aldec DO-254/CTS and accepted our test results, and the audit passed without any findings,” describes Moshe Porian, logic design verification group leader at Elbit Systems Aerospace Division. “This is the first time in Elbit’s history that we have been able to bring more than five FPGA devices to the audit. Aldec helped us solve several of our verification challenges, and delivered quick and professional responses for all our requests.”
“Elbit needed to implement robustness testing for their design assurance level (DAL) A FPGAs. By executing the simulation environment in hardware using DO-254/CTS boards, Elbit was able to catch bugs which gave them verification credits for robustness,” says Zibi Zalewski, general manager of Aldec’s Hardware Products Division. “Additionally, we also provided testing capabilities for abnormal operating conditions with input voltage and clock frequency variations that are all scriptable. This enabled automated testing of all FPGA requirements after each change of code, including advanced results comparison functions.”
DO-254/CTS is a customized hardware and software platform that augments target board testing to increase verification coverage by test and satisfy the verification objectives of DO-254/ED-80. The target design runs at-speed in the target device mounted on the custom daughter board. The simulation testbench is used as test vectors to enable requirements-based testing with FPGA pin-level controllability and visibility necessary to implement normal range and abnormal range tests. The FPGA testing results are captured at-speed and displayed using a simulator waveform viewer for advanced analysis and documentation. For more information, go to www.aldec.com/do254.
Aldec Inc. in Henderson, Nev., is a 30-year Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, Requirements Management, DO-254 Functional Verification, and Military/Aerospace solutions.