Aldec offers finite state machine coverage for verification of safety-critical FPGAs

HENDERSON, Nev. Aldec Inc. is introducing the latest version of its mixed-language, field-programmable gate array (FPGA) design and simulation platform, Active-HDL 10.4, providing finite-state machine (FSM) coverage for FPGA engineers developing safety-critical FPGAs.

Jan 20th, 2017
Aldec offers finite state machine coverage for verification of safety-critical FPGAs
Aldec offers finite state machine coverage for verification of safety-critical FPGAs

HENDERSON, Nev.Aldec Inc. is introducing the latest version of its mixed-language, field-programmable gate array (FPGA) design and simulation platform, Active-HDL 10.4, providing finite-state machine (FSM) coverage for FPGA engineers developing safety-critical FPGAs.

Safety-critical design assurance guidance and standards, such as those defined in RTCA/DO-254 for Avionics, recommend the use of FSM coverage as part of the overall verification process.

“FPGAs in the field used in safety-critical applications must function reliably as defined in the requirements under all foreseeable environmental conditions,” says Radek Nawrot, Aldec software product manager. “This puts significant pressure on verification engineers which can be alleviated through use of the recommended FSM Coverage, a valuable addition to Aldec’s verification tools.”

FSM coverage enables users to determine which states and transitions in the state machine diagram have been executed during simulation. To collect the FSM coverage statistics, the HDL design code has to include SystemVerilog or Aldec proprietary pragmas indicating which constructs represent components of the state machine. The pragmas used in the HDL code are included in additional lines of comments and interpreted by the coverage engine.

FSM coverage statistics can be stored in the Aldec Coverage Database (ACDB) files and presented in a textual or HTML report along with OSVVM Functional Coverage providing complete structural coverage and functional coverage with test results merging, ranking, and analysis.

Active-HDL is an FPGA veteran tool that has been helping FPGA designers for almost two decades. It is an HDL-based FPGA design and simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language simulation solution interfaces with nearly 120 third-party vendor tools and provides FPGA designers a single platform that can be used independently. Active-HDL 10.4 supports design creation and simulation of the newest industry-leading FPGA devices from Intel FPGA (Altera), Lattice, Microsemi (Actel), and Xilinx.

The 10.4 release of Active-HDL also includes numerous new features, enhancements, and performance optimizations.

Established in 1984, Aldec provides Electronic Design Verification and offers a patented technology suite, including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions, and Military/Aerospace solutions.

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