FPGA with an integrated AFDX avionics databus for commercial aircraft offered by MEN Micro

BLUE BELL, Pa. 23 Feb. 2015. MEN Micro Inc. in Blue Bell, Pa., is introducing the CS1 field-programmable gate array (FPGA) chip with an integrated AFDX avionics databus protocol for commercial aircraft data networking.

Feb 23rd, 2015
By Intelligent Aerospace staff
By Intelligent Aerospace staff

BLUE BELL, Pa. 23 Feb. 2015. MEN Micro Inc. in Blue Bell, Pa., is introducing the CS1 field-programmable gate array (FPGA) chip with an integrated AFDX avionics databus protocol for commercial aircraft data networking.

The customizable CS1 enables users to build AFDX-based communication systems independent of a form factor. The FPGA can be installed on the boards of an AFDX end system to eliminate the need of an additional module to integrate the AFDX protocols, which send information between avionics subsystems in airborne applications.

The chip is a DO-254-compliant FPGA certifiable up to DAL-A, with DAL-D certification support package available in March 2015. Developed according to ARINC 664P7-1, and in consideration of the specific Airbus and Boeing AFDX requirements, the CS1 can be used in applications of both airplane suppliers.

Its flash-based architecture with tripled redundant logic enables the FPGA to meet safety-critical demands like radiation hardness and real-time capability.

Related: Rugged computer for planes, trains, building equipment introduced by MEN Micro

The CS1 is also offered in MEN Micro’s P522 PMC I/O mezzanine card–available as a COTS product that can be used as an alternative to PMCs already on the market or for evaluation purposes.

The CS1 is customizable to enable such functions as gateway solutions including AFDX-to-CAN, AFDX-to-standard Ethernet or AFDX-to-ARINC 429. The host driver with an ARINC-653 compliant port API (Application Programming Interface) prevents the influence of critical and non-critical applications within one complete system.

The CS1 supports two full duplex AFDX networks based on standard IEEE 802.3 Ethernet and applies protocol stack implementation. It has as many as 255 receive VLs (Virtual Links) and 64 transmit VLs.

The integrated SNMP/ICMP protocols support the host CPU with the network management, enabling higher performance from the CPU. For more information contact MEN Micro online at www.menmicro.com.

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